/**
  ******************************************************************************
  * @file    gt32f030_dma.h
  * @author  GT Application Team
  * @version V1.0.0
  * @date    03-January-2025
  *       
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 Giantec Semicondutor Inc</center></h2>
  *
  *             http://www.giantec-semi.com/
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GT32F030_DMA_H
#define __GT32F030_DMA_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "gt32f030.h"

/** @addtogroup GT32F030_StdPeriph_Driver
  * @{
  */

/** @addtogroup DMA
  * @{
  */ 

/* Exported macro ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup DMA_Exported_Constants
  * @{
  */
	 
	 

typedef enum
{ 
  DMA_Channel0 = 0x01,
  DMA_Channel1 = 0x02,
	DMA_Channel2 = 0x04

}DMAChannel_TypeDef;
#define IS_DMA_CHANNEL(CHN) (((CHN) == DMA_Channel0) || \
                             ((CHN) == DMA_Channel1) || \
                             ((CHN) == DMA_Channel2))

typedef enum
{ 
  DMATransferType_M2M  = 0x00,
  DMATransferType_M2P  = 0x01,
	DMATransferType_P2M  = 0x02,
	DMATransferType_P2P  = 0x03
}DMATransferType_TypeDef;
#define IS_DMATransferType(TYPE) (((TYPE) == DMATransferType_M2M) || \
																	((TYPE) == DMATransferType_M2P) || \
																	((TYPE) == DMATransferType_P2M) || \
																	((TYPE) == DMATransferType_P2P))

typedef enum
{ 
  DMAAddrDir_Inc  = 0x00,
  DMAAddrDir_Dec  = 0x01,
	DMAAddrDir_Hold = 0x02
}DMAAddrDir_TypeDef;
#define IS_DMAAddrDir(Dir) (((Dir) == DMAAddrDir_Inc) || \
                            ((Dir) == DMAAddrDir_Dec) || \
                            ((Dir) == DMAAddrDir_Hold))

typedef enum
{ 
  DMADataWidth_8bit  = 0x00,
  DMADataWidth_16bit = 0x01,
	DMADataWidth_32bit = 0x02
}DMADataWidth_TypeDef;
#define IS_DMA_DataWidth(DataWidth) (((DataWidth) == DMADataWidth_8bit)  || \
                                     ((DataWidth) == DMADataWidth_16bit) || \
                                     ((DataWidth) == DMADataWidth_32bit))

typedef enum
{ 
  DMAPrior_Low  = 0x00,
  DMAPrior_Mid  = 0x01,
	DMAPrior_High = 0x02
}DMAPrior_TypeDef;
#define IS_DMA_Prior(CHN) (((Prior) == DMAPrior_Low) || \
                           ((Prior) == DMAPrior_Mid) || \
                           ((Prior) == DMAPrior_High))

typedef enum
{ 
  DMAHs_HS0  = 0x00,
  DMAHs_HS1  = 0x01,
	DMAHs_HS2  = 0x02,
	DMAHs_HS3  = 0x03,
  DMAHs_HS4  = 0x04,
	DMAHs_HS5  = 0x05
}DMAHs_TypeDef;
#define IS_DMA_Hs(Hs) (((Hs) == DMAHs_HS0) || \
                       ((Hs) == DMAHs_HS1) || \
                       ((Hs) == DMAHs_HS2) || \
                       ((Hs) == DMAHs_HS3) || \
                       ((Hs) == DMAHs_HS4) || \
                       ((Hs) == DMAHs_HS5))


typedef struct 
{
  DMAChannel_TypeDef    	 	DMA_Channel; 
	unsigned int           		DMA_BlockTS;
	unsigned int           		DMA_SrcAddr;
	unsigned int           		DMA_DstAddr;
	DMATransferType_TypeDef   DMA_TransferType;
  DMAAddrDir_TypeDef    		DMA_SrcAddr_Dir;	
	DMAAddrDir_TypeDef    		DMA_DstAddr_Dir;	
	DMADataWidth_TypeDef  		DMA_SrcDataWidth;
	DMADataWidth_TypeDef  		DMA_DstDataWidth;
	FunctionalState       		DMA_Intr_Cmd;
	FunctionalState       		DMA_DstReload_Cmd;
	FunctionalState       		DMA_SrcReload_Cmd;
	DMAHs_TypeDef         		DMA_DstHsSelect;
	DMAHs_TypeDef         		DMA_SrcHsSelect;
  DMAPrior_TypeDef      		DMA_Prior;
}DMA_ChnInitTypeDef;


typedef enum
{ 
  DMAHS0Source_TIM2CC1     = 0x00,
  DMAHS0Source_TIM2Update  = 0x01,
	DMAHS0Source_QSPI2RX     = 0x02,
	DMAHS0Source_QSPI2TX     = 0x03
}DMAHS0Source_TypeDef;

typedef enum
{ 
  DMAHS1Source_TIM2CC1     = 0x00,
  DMAHS1Source_TIM2Update  = 0x01,
	DMAHS1Source_QSPI2RX     = 0x02,
	DMAHS1Source_QSPI2TX     = 0x03
}DMAHS1Source_TypeDef;

typedef enum
{ 
  DMAHS2Source_TIM2CC3  = 0x00,
  DMAHS2Source_TIM2CC2  = 0x01,
	DMAHS2Source_QSPI1RX  = 0x02,
	DMAHS2Source_QSPI1TX  = 0x03
}DMAHS2Source_TypeDef;

typedef enum
{ 
  DMAHS3Source_TIM2CC3  = 0x00,
  DMAHS3Source_TIM2CC2  = 0x01,
	DMAHS3Source_QSPI1RX  = 0x02,
	DMAHS3Source_QSPI1TX  = 0x03
}DMAHS3Source_TypeDef;

typedef enum
{ 
  DMAHS4Source_TIM2Trg  = 0x00,
  DMAHS4Source_TIM2COM  = 0x01,
	DMAHS4Source_TIM2CC4  = 0x02,
	DMAHS4Source_ADC  = 0x03
}DMAHS4Source_TypeDef;

typedef enum
{ 
  DMAHS5Source_TIM2Trg  = 0x00,
  DMAHS5Source_TIM2COM  = 0x01,
	DMAHS5Source_TIM2CC4  = 0x02,
	DMAHS5Source_ADC  = 0x03
}DMAHS5Source_TypeDef;

typedef struct 
{
	DMAHS0Source_TypeDef  DMA_HS0Source;
  DMAHS1Source_TypeDef  DMA_HS1Source;
	DMAHS2Source_TypeDef  DMA_HS2Source;
	DMAHS3Source_TypeDef  DMA_HS3Source;
	DMAHS4Source_TypeDef  DMA_HS4Source;
	DMAHS5Source_TypeDef  DMA_HS5Source;
}DMA_HSInitTypeDef;

typedef enum 
{
	DMAIT_Tfr    = 0x00,
  DMAIT_Block  = 0x01,
	DMAIT_Error  = 0x02
}DMAIT_TypeDef;

/* Exported functions --------------------------------------------------------*/
void DMA_DeInit(void);
void DMA_ChannelInit(DMA_ChnInitTypeDef* DMA_ChnInitStruct);
void DMA_HSInit(DMA_HSInitTypeDef* DMA_HSInitStruct);
void DMA_Cmd(FunctionalState NewState);
void DMA_ChannelCmd(DMAChannel_TypeDef chn,FunctionalState NewState);
void DMA_ITConfig(DMAIT_TypeDef DMA_IT, DMAChannel_TypeDef chn, FunctionalState NewState);
FlagStatus DMA_GetPendingBit(DMAIT_TypeDef DMA_IT, DMAChannel_TypeDef chn);
void DMA_ClearPendingBit(DMAIT_TypeDef DMA_IT, DMAChannel_TypeDef chn);
#ifdef __cplusplus
}
#endif

#endif /* __GT32F030_DMA_H */

/**
  * @}
  */ 

/**
  * @}
  */ 

/************************ (C) COPYRIGHT Giantec Semicondutor Inc *****END OF FILE****/
